Presently available dynamic random access memory devices (DRAMs), and their derivatives such as video RAMs (VRAMs), cache DRAMs and window RAMs, are typically designed around a well-established architecture. In the basic architecture, the memory cells are arranged as a rectangular array of m number of rows and n number of columns, with each row associated with a conductive rowline (wordline) and each column associated with a conductive column line (bitline). Row decoder circuitry, including a row address decoder, is coupled to the wordlines and charges the wordline of an addressed row to allow access to the cells of that row. Sense amplifiers are coupled to each of the bitlines for reading, writing and refreshing the data in the cells along the addressed row. Column decoder circuitry is then coupled to the sense amplifiers to allow reading and writing of data into a specific cell or cells (a "location") along the addressed row in response to a column address.
The traditional DRAM is controlled by a number of conventional control signals. In addition power and ground inputs, the typical DRAM includes a random data port of a selected bit-width, a multiplexed address port of a bit-width appropriate to the size of the array, inputs for receiving row address and column address strobes (RAS and CAS) and inputs for receiving read/write (R/W) and output enable (OE) control signals. Normally, to access (read from or write to) a location in the array, a row address in first presented to the address port and latched in with RAS. Once the row address is latched in, a column address is presented at the data port and latched in with CAS. Some predetermined time after receipt of the column address, access is gained to the addressed location through the data port. The read/write control signal determines if data is being read out or written in to the addressed location. The output enable control signal enables the output buffers to drive the data port during a read.
To accommodate all the required addresses, control signals and data inputs and outputs, corresponding number of pins are required for the DRAM packaging. For example, the package for the typically 1 megabit by 16 DRAM (i.e., each location has 16 cells which are accessed per column address) requires 16 input port pins, 12 address port pins, 1 or 2 ground pins, 1 or 2 power pins, and 1 pin each for RAS, CAS, R/W and OE, for a total of 34 or 36 pins. Some DRAM devices, such as those having a CAS split into upper and lower bytes, may include up to 38 pins for the same size (1 megabit by 16) memory. Most DRAM packages are standardized and have either 40, 42, 44, 48, or 64 pins. Thus, a number of unused "no connect" (NC) pins a commonly found on packaged DRAMs. While these unused pins are available to provide additional functionality to a given DRAM device, this feature is typically not taken advantage of.
As discussed briefly above, data in a DRAM is typically accessed on a word by word basis. These words may for example be of 1, 4, 8, 16, 32 or 64 bits in lengths. The accesses themselves may be random, pages, serial or nibbled. The page mode is particularly useful in applications, such as display data processing, where blocks of data are often required at a time. In the page mode, a row address is presented to address port and latched in with RAS to select a given row in the array. A column address is next presented to the address port and latched in CAS to select a first column or group of columns allowing access to a first word along the selected row. Column decode (static or dynamic) circuitry then increments from the received column address to generate a sequence of column addresses to adjacent column or group of columns, thereby allowing access to a "page" of words along the same selected row.
The advantages of using the page mode become apparent in light of the manner in which most data processing systems currently operate. Often, spacial locality and/or temporal locality of data in memory is maintained for efficiency. For example, a central processing unit (CPU) may execute an instruction sequence which mostly operates adjacent blocks of data in memory. In some cases, accesses to and from such "spatially contiguous" blocks may take place during 90% of the execution time. The CPU may also execute loops of instructions and subinstructions which repeatedly operate on the same blocks of data in memory. In this case, "temporal locality" is being maintained. The page mode is preferable in each of these cases since a number of words are accessed during a single RAS random cycle (i.e., per row address).
Presently, DRAM performance in the page mode is limited by page length. The length of a page is determined primarily by the capabilities of the peripheral circuitry and the length of the rows in the cell array. For example, a 16 megabit memory may be organized as "k rows and k columns" (in an actual implementation the array is 4,096 rows by 4,096 columns). The maximum length of any page in this case is therefore k (4,096) bits, irrespective of the number of bits per word accessed per column address ("CAS cycle"). As a result, each time the data for an entire row has been accessed, a complete new RAS cycle must be performed to address the next row. In other words, no more than one row can be paged out at a time before interruption by another "random" cycle (RAS cycle). Significantly, the time required for each RAS cycle is substantially longer than that required to access a page, typically 130 nanoseconds versus 40 nanoseconds for the first page. In other words, the first page after RAS goes active typically requires 70-80 nanoseconds and each subsequent page (CAS cycle) along that row typically requires approximately 40 nanoseconds. Thus, with currently available DRAM, substantial amounts of time a required to access a block of cells spanning multiple rows, and in particular, all the cells in the array.
Thus, the need has arisen for circuits, systems and methods for improving page mode accesses in DRAMs and their derivatives. Such circuits, systems and methods should allow for page mode access of blocks of cells spanning multiple rows and even provide for the page mode access to all the cells in the cell array. In implementing the additional functionality, any necessary control signals generated off-chip should advantageously use the available "NC" connections already available in standard DRAM packaging.